info:eu-repo/semantics/conferencePoster
Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation (poster)
Fecha
2018-03Registro en:
F. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, and N. Hakim, “Direct optimization of a PCI Express link equalization in industrial post-silicon validation,” in IEEE Latin American Test Symp. (LATS 2018), Sao Paulo, Brazil, Mar. 2018 (poster).
978-1-5386-1473-0
Autor
Rangel-Patiño, Francisco E.
Rayas-Sánchez, José E.
Vega-Ochoa, Edgar A.
Hakim, Nagib