info:eu-repo/semantics/article
A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation
Fecha
2016-12Registro en:
F.E. Rangel-Patino, A. Viveros-Wacher, J.E. Rayas-Sánchez, E.A. Vega-Ochoa, I. Duron-Rosales, and N. Hakim, “A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-4. DOI: 10.1109/LAMC.2016.7851268
978-1-5090-4288-3
Autor
Rangel-Patiño, Francisco E.
Viveros-Wacher, Andrés
Rayas-Sánchez, José E.
Vega-Ochoa, Edgar A.
Duron-Rosales, Ismael
Hakim, Nagib