masterThesis
Redes em chip irregulares para tolerância a falhas e atendimento de tempo real
Fecha
2021-01-28Registro en:
CARDOSO, Elisio Breno Garcia. Redes em chip irregulares para tolerância a falhas e atendimento de tempo real. 2021. 109f. Dissertação (Mestrado em Sistemas e Computação) - Centro de Ciências Exatas e da Terra, Universidade Federal do Rio Grande do Norte, Natal, 2021.
Autor
Cardoso, Elisio Breno Garcia
Resumen
Network-on-chip emerged due to the need to efficiently communicate the cores from a
multiprocessor systems on a chip. Since then, they have become the main communication
paradigm for this type of system, with several architectural models being proposed over
the years to meet restrictions related to median latency, network area, energy consumption, among others. The projects also cover the network architecture, with the generation
of topologies that provide optimized performance for specific applications. This work
proposes a heuristic for the generation of fault-tolerant topologies capable of delivering
real-time packets via an alternative path within the network even if a link fail. To evaluate the proposed solution, a SystemC simulator NoC42 has been modified to support irregular topologies, real-time packets, a routing algorithm based in a routing table and
a fault injector.