masterThesis
Mecanismo de tolerância a falhas através de escalonamento para uma arquitetura reconfigurável de grão grosso
Fecha
2015-03-16Registro en:
SANTOS, Eliselma Vieira dos. Mecanismo de tolerância a falhas através de escalonamento para uma arquitetura reconfigurável de grão grosso. 2015. 75f. Dissertação (Mestrado em Sistemas e Computação) - Centro de Ciências Exatas e da Terra, Universidade Federal do Rio Grande do Norte, Natal, 2015.
Autor
Santos, Eliselma Vieira dos
Resumen
The continuous evolution of integrated circuit technology has allowed integrating
thousands of transistors on a single chip. This is due to the miniaturization
process, which reduces the diameter of wires and transistors. One drawback of
this process is that the circuit becomes more fragile and susceptible to break,
making the circuit more susceptible to permanent faults during the manufacturing
process as well as during their lifetime. Coarse Grained Reconfigurable
Architectures (CGRAs) have been used as an alternative to traditional
architectures in an attempt to tolerate such faults due to its intrinsic hardware
redundancy and high performance. This work proposes a fault tolerance
mechanism in a CGRA in order to increase the architecture fault tolerance even
considering a high fault rate. The proposed mechanism was added to the
scheduler, which is the mechanism responsible for mapping instructions onto the
architecture. The instruction mapping occurs at runtime, translating binary code
without the need for recompilation. Furthermore, to allow faster implementation,
instruction mapping is performed using a greedy module scheduling algorithm,
which consists of a software pipeline technique for loop acceleration. The results
show that, even with the proposed mechanism, the time for mapping instructions
is still in order of microseconds. This result allows that instruction mapping
process remains at runtime. In addition, a study was also carried out mapping
scheduler rate. The results demonstrate that even at fault rates over 50% in
functional units and interconnection components, the scheduler was able to map
instructions onto the architecture in most of the tested applications.