A petri net based timing model for hardware/software co-design of digital systems

Trabalho apresentado em evento

Fecha

2004-12-01

Registro en:

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, v. 1, p. 65-68.

http://hdl.handle.net/11449/67969

10.1109/APCCAS.2004.1412692

WOS:000227668700017

2-s2.0-13444251353

0000-0003-1086-3312

http://repositorioslatinoamericanos.uchile.cl/handle/2250/3917554

Autor

Universidade Estadual Paulista (Unesp)

Universidade Estadual de Campinas (UNICAMP)

Institución

Universidade Paulista Júlio de Mesquita Filho (Brasil)

Resumen

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.

Materias

Computational complexity

Field programmable gate arrays

Mathematical models

Timing devices

Cooperative design (co-design)

Digital systems

Merlin's time model

Networks on chip (NoC)

Petri nets

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