| dc.creator | Vitola, Jaime | |
| dc.creator | Pedraza, Cesar | |
| dc.creator | Martínez, Jose I. | |
| dc.creator | Sepulveda, Johanna | |
| dc.date.accessioned | 2020-01-21T12:35:31Z | |
| dc.date.accessioned | 2022-09-28T14:58:43Z | |
| dc.date.available | 2020-01-21T12:35:31Z | |
| dc.date.available | 2022-09-28T14:58:43Z | |
| dc.date.created | 2020-01-21T12:35:31Z | |
| dc.date.issued | 2014-10-17 | |
| dc.identifier | http://hdl.handle.net/11634/20886 | |
| dc.identifier | https://doi.org/10.1109/CWCAS.2014.6994608 | |
| dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/3667681 | |
| dc.description.abstract | The use of evolutionary algorithms in the boolean
synthesis is an interesting technique to generate hardware structures with multiple restrictions. However, one characteristic of
these algorithms is their high computational load. This paper
presents the implementation of a parallel cartesian genetic
programming (CGP) for boolean synthesis on a FPGA-CPU
based platform. Power consumption and critical path restrictions
were included into the algorithm in order to generate structures
to solve any problem. As results a 2-bit comparator is presented,
as well as response time and data transitions probability | |
| dc.rights | http://creativecommons.org/licenses/by-nc-sa/2.5/co/ | |
| dc.rights | Atribución-NoComercial-CompartirIgual 2.5 Colombia | |
| dc.title | Cartesian genetic algorithm for boolean synthesis with power consumption restriction | |
| dc.type | Generación de Nuevo Conocimiento: Artículos publicados en revistas especializadas - Electrónicos | |
