Now showing items 1-10 of 57
Modeling and measuring double-frequency jitter in one-way master-slave networks
(ELSEVIER SCIENCE BV, 2009)
The double-frequency jitter is one of the main problems in clock distribution networks. In previous works, sonic analytical and numerical aspects of this phenomenon were studied and results were obtained for one-way ...
Chaotic Synchronization in Discrete-Time Systems Connected by Bandlimited Channels
(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2011)
Due to the broadband characteristic of chaotic signals, many of the methods that have been proposed for synchronizing chaotic systems do not usually present a satisfactory performance when applied to bandlimited communication ...
Design constraints for third-order PLL nodes in master-slave clock distribution networks
(ELSEVIER SCIENCE BV, 2010)
Clock signal distribution in telecommunication commercial systems usually adopts a master-slave architecture, with a precise time basis generator as a master and phase-locked loops (PLLs) as slaves. In the majority of the ...
Comparing lock-in ranges and transient responses of second- and third-order phase-locked loops in master-slave clock distribution networks
(ELSEVIER GMBH, URBAN & FISCHER VERLAG, 2008)
The distribution of clock signals throughout the nodes of a network is essential for several applications. in control and communication with the phase-locked loop (PLL) being the component for electronic synchronization ...
Predicting efficiency in master-slave grid computing systems
(Oxford University Press - OUPOxford, 2013-06)
This work reports a quantitative analysis to predicting the efficiency of distributed computing running in three models of complex networks: Barabási-Albert, Erdõs-Rényi and Watts-Strogatz. A master-slave computing model ...
Modeling and Filtering Double-Frequency Jitter in One-Way Master-Slave Chain Networks
(IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2010)
One-way master-slave (OWMS) chain networks are widely used in clock distribution systems due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs), double-frequency jitter (DFJ) caused by ...
LIN 1.3 driver implementation in a DEMO9S12XEP100 Board
Speedup and scalability analysis of Master-Slave applications on large heterogeneous clusters
(Elsevier B.V., 2007-11-01)
Although cluster environments have an enormous potential processing power, real applications that take advantage of this power remain an elusive goal. This is due, in part, to the lack of understanding about the characteristics ...
Mutually connected phase-locked loop networks: dynamical models and design parameters
(INST ENGINEERING TECHNOLOGY-IET, 2008)
Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented ...