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Synthesis and Optimization of Majority Expressions through a Mathematical Model
(Ieee, 2020-01-01)
In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth ...
Synthesis and Optimization of Majority Expressions through a Mathematical Model
(2020-08-01)
In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth ...
Correction of functional logic programs
(SPRINGER, 2003-01-01)
We propose a new methodology for synthesizing correct functional logic programs. We aim to create an integrated development environment in which it is possible to debug a program and correct it automatically. We start from ...
A methodology for the synthesis to logical netlist of an ASIC
(Instituto Tecnológico de Costa Rica, 2017)
The advances in technology for manufacturing ASICs allow more features to be added.
As result, and depending on the architecture of the ASIC, more functional blocks do exist
to support such additional features. This imply ...
Comparative Analysis of the Efficiency of the Transformation Algorithm and the Cycles Decomposition Algorithm for the Synthesis of Ternary Reversible Circuits
(Old City Publishing Inc, 2022-01-01)
The design algorithm for binary reversible circuits based on the decomposition of permutations as cascade of disjoint cycles (CD algorithm) is extended to the ternary domain. Its performance is evaluated using as a benchmark ...
Discrete wavelet transform signal analyzer
(2007-10-01)
This paper addresses the problem of processing biological data, such as cardiac beats in the audio and ultrasonic range, and on calculating wavelet coefficients in real time, with the processor clock running at a frequency ...