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Mostrando ítems 1-10 de 11
An explicit parallelism study based on thread-level speculation
(Centro Latinoamericano de Estudios en Informática, 2014)
Using Hardware Transactional Memory to Implement Speculative Privatization in OpenMP
(2022-01-01)
Loop Thread-Level Speculation on Hardware Transactional Memories is a promising strategy to improve application performance in the multicore era. However, the reuse of shared scalar or array variables introduces constraints ...
A Proposal for Supporting Speculation in the OpenMP taskloop Construct
(Springer, 2019-01-01)
Parallelization constructs in OpenMP, such as parallel for or taskloop, are typically restricted to loops that have no loop-carried dependencies (DOALL) or that contain well-known structured dependence patterns (e.g. ...
Evaluating And Improving Thread-level Speculation In Hardware Transactional Memories
(IEEENew York, 2016)
Cache-based Cross-iteration Coherence For Speculative Parallelization
(IEEE Computer Society, 2013)
FGSCM: A Fine-Grained Approach to Transactional Lock Elision
(2017-11-08)
Speculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock operation and enabling multiple threads to execute concurrently. In case of inconsistencies, the ...
Increasing the reliability and applicability of measurement-based probabilistic timing analysis
(2019)
Conforme a complexidade das arquiteturas computacionais aumenta para melhorar desempenho ou reduzir custos, o uso de processadores modernos em Sistemas de Tempo Real (STRs) é prejudicado cada vez mais pelo surgimento de ...