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GR-Noise Characterization of Ge pFinFETs with STI First and STI Last Processes
(2016-09-01)
This letter characterizes the generation-recombination noise of Ge pFinFETs, for three different integration schemes: shallow trench isolation (STI) first strained devices; STI last for relaxed and strained ones. It is ...
Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes
(2016-10-13)
The effective hole mobility of long strained Ge pFinFETs, fabricated with shallow trench isolation (STI) first and last approaches, is systematically evaluated from room temperature down to 77 K, from planar-like (100 nm) ...
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes
(2017-01-03)
One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs ...
Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes
(Ieee, 2016-01-01)
One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 ...
Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes
(Ieee-inst Electrical Electronics Engineers Inc, 2016-10-01)
An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from ...
Ground plane impact on the threshold voltage of relaxed ge pfinfets
(2018-10-26)
In this paper the Ground Plane (GP) influence on the threshold voltage of Ge pFinFET devices is investigated. In order to explain the experimental threshold voltage variation with fin width, TCAD simulations have been ...
Low temperature effect on strained and relaxed Ge pFinFETs STI last processes
(2016-01-01)
Ge pFinFETs, fabricated either with an STI last process on a Geon-Si virtual substrates or a SiGe strain-relaxed buffer, have been systematically evaluated at temperatures from 200 K down to 77 K. In the first cases, the ...
Ground Plane Impact on the Threshold Voltage of Relaxed Ge pFinFETs
(Ieee, 2018-01-01)
In this paper the Ground Plane (GP) influence on the threshold voltage of Ge pFinFET devices is investigated. In order to explain the experimental threshold voltage variation with fin width, TCAD simulations have been ...
Low temperature influence on long channel STI last process relaxed and strained Ge pFinFETs
(2018-03-07)
The operation of germanium p-type channel FinFETs with two types of different channels, namely, relaxed and strained, is compared from room temperature down to 77 K. The most interesting finding is a higher ION over IOFF ...
CT&I no Brasil: um olhar sobre o processo inovativo nacional contemporâneo
(Florianópolis, SC, 2021)