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A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication
(Institute of Electrical and Electronics Engineers (IEEE), 2003-04-01)
An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting ...
A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication
(Institute of Electrical and Electronics Engineers (IEEE), 2003-04-01)
An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting ...
Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process
(Springer, 2010-10-01)
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is ...
Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process
(Springer, 2010-10-01)
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is ...
A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency
(2001-01-01)
A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage ...
FGMOS four-quadrant analog multiplier
(2012)
This paper presents a four-quadrant analog multiplier. The architecture of the multiplier is designed with floating-gate CMOS transistors formed by squaring and current mirrors circuits. The results shown are accurate and ...
Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process
(IEEE, 2007-01-01)
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is ...